NoC Simulator

First of all what was the goal of my thesis?
Design and write a Simulator for NoC.

What's NoC?
Network on chip.
They are an alternative to the communications on chip. NoCs are based on networks instead using traditional buses or peer to peer connections.

What are the problems?
The classic(buses, p2p) interconnection networks has a lot of problems in the next communication infrastructures.
The key point is how the design of an integrated circuit is changing to a model with a lot of IPs.


Peer-to-Peer(p2p):
Not reusable.
bad scalability (Area cost increase a lot with the number of IPs)




Buses:
Reusable
One transaction at a time.
bad scalability(Performance divided for the number of IPs)


Global problems:
Long lines.
Skew.
With a lot of IPs, the power consumption of the interconnection network become important.

Why the model is changing into a one with more IPs and the number of IPs will grow and grow?
As you may know a chip has different independent cores or IPs with different functions.
For example an MPEG2 Integrated Circuit (IC) has different blocks for:
-transform coding with 8x8 DCT
-quantization of the DCT coefficients
-prediction of the DC coefficient
-code bitstream elements
-etc.
Or in the other hand, if we look to a more heterogeneous IC, we could have an IP for MPEG codin and others units for the DSP, UARTs, or general processing.

This are the facts:
-Design cost is growing and growing (a)
-Time-in-the-Market of a product is smaller than ever (b)
-(a)(b) -> A design needs to be used in several generations or different families for being amortized. (1)
-The Time-to-Market is a key point. Time for design is smaller than ever. (2)
-(1)(2) -> The design process is changing to a one that reuse a lot of IPs. The number of IPs per chips is growing and growing.